A finished gate structure (such as a finished gate or transistor gate) is the transistor terminal that modulates channel conductivity. Two principle approaches for forming semiconductor device gate structures are the gate-first and gate-last process approaches.
During fabrication of gate structures for, for instance, complementary metal-oxide-semiconductor (CMOS) technology, gate-first fabrication has traditionally been employed. In a gate-first fabrication approach, a conductor is provided over a gate dielectric, and then patterned (i.e., etched) to form one or more gate structures. After forming the gate structures, source and drain features of the semiconductor devices are provided.
As transistors continue to decrease in size and the number of transistors per unit of microchip grows, a MOSFET pitch of the transistors scales down (e.g., under 22 nm) and a thickness of a SiN spacer of a gate structure also scales to provide a large enough contact area for a source/drain thereof. However, such a thinner spacer induces higher parasitic capacitance which is undesirable because such high capacitance can reduce a circuit speed. The parasistic capacitance of the circuit increase may cause slower ring oscillator (RO) speed and eventually lower circuit working frequency. With higher effective capacitance (CEFF) of RO, circuit ac performance may degraded and there may be more power consumption during dynamic operation.
More recently, the gate-last approach (or replacement metal gate (RMG) approach), has been employed. In the gate-last approach, a sacrificial (or dummy) gate material is provided and patterned (i.e., etched) to define one or more sacrificial gates. The one or more sacrificial gates are subsequently replaced with, for instance, a metal gate, after source and drain features of the devices have been formed. The sacrificial gate material holds the position for the subsequent metal gate to be formed. For instance, an amorphous silicon (a-Si) or polysilicon sacrificial gate may be patterned and used during initial processing until high-temperature annealing to activate the source and drain features has been completed. Subsequently, the a-Si or polysilicon may be removed and replaced with the final metal gate.
Accordingly, a need exists for improved systems and methods for forming semiconductor device gate structures to reduce parasitic losses.